Integrated circuits face a constraint for reduced effective area and power while increasing performance (e.g., enhanced data rates with reduced power consumption at a reduced cost). Receivers are ubiquitous devices used as buffers for signals going from a processor to a memory or vice versa. The precise control of a voltage threshold for a signal transition in a receiver affects the timing of the receiver, the jitter and the bit-error rate (BER) of the system. Accordingly, some approaches to address these issues include digitally controlled calibration of the voltage threshold in a receiver. However, digitally controlled calibration is typically valid for a specific power-voltage and temperature (PVT) environment. Therefore, this digitally controlled calibration scheme naturally requires frequent pause of the system because those PVT environments change over time. Further, digitally controlled calibration schemes typically take a long time to complete, thereby interfering with high data rate transfer in demanding environments (e.g., read/write commands in random access memories). Some approaches using auto-zeroing are not compatible with NRZ signal schemes, which are commonly used in high data rate operations.
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